Output of first NAND gate with input A

$$\eqalign{ & = \overline {A.A} \cr & = \overline A + \overline A \cr & = \overline A \cr} $$

Similarly, Output of first NAND gate with input B

$$ = \overline B $$

$$\eqalign{ & {Y_1} = \overline {\overline A .\overline B } \cr & = \overline {\overline A } + \overline {\overline B } \cr & = A + B \cr} $$

$$\eqalign{ & Y = \overline {\left( {A + B} \right).\left( {A + B} \right)} \cr & = \overline {\left( {A + B} \right)} + \overline {\left( {A + B} \right)} \cr & = \overline {\left( {A + B} \right)} \cr} $$

So, given logic gates circuit is a NOR gate.